Start with the 'CleverLoad.pdf' document then if you're still interested explore the operations manual in the 'Ops Manual' folder.

This was a one-off project so the documentation isn't as complete as I would like.  The version 1.3b PCB was functional save for problems with the clock, it didn't keep time well during storage so changes were made using SMD breadboarding as can be seen in one of the pictures in the photo gallery.  The version 1.4a schematic reflects these changes but the PCB was never made.  Additionally the 50ohm termination and pickoff circuitry needs attention to detail to function well up to 1300MHz.  Use the configuration shown in the version 1.4a schematic.  Note that two 2490 ohm 1206 resistors were used in series instead of one larger 5k.  The tent style SMD assembly structure minimized parasitic capacitance associated with the resistor and improved the frequency responce. There's a picture of how to do this in the Picutre Gallery folder. Also make sure to use C38 the RF cap from the junction of R30 and R3 to flatten the structure's frequency responce. It's shown in the picture gallery capacitors are installed after the zero ohm jumper (not used in the 1.4a circuit) to ground. The Cadock 50 ohm resistor also has a shield over the bottom and top, uses a thick thermal pad under the device for heatsinking to minimize capacitance to ground. The 'input' lead of the resistor also is formed into an inductor as shown in the picture gallery to form part of a Chebyshev filter in conjunction with parasitic caps to ground.

Also the device has the hardware to perfom datalogging but the software to support that feature was never implemented.

It's been a few years since I put this device together but if you have any questions I'll try and answer them...if I can remember that is...you can send me an email...ve3czo(at)gmail.com